Broadly, a phase lock loop is considered to be a kind of filter that passes signals and rejects noise. Gardner, "Phase Lock Techniques," John Marley & Sons (New York, 1979). Stated differently, the task of the phase lock loop is typically to reproduce an original signal while removing as much noise present in the signal as possible. To reproduce the signal, the phase lock loop makes use of a local oscillator, typically a voltage controlled oscillator (VCO), whose frequency is very close to that of the expected signal. The VCO output and incoming signal waveforms are compared with one another by a phase detector whose output indicates instantaneous phase difference (i.e. phase error). In order to suppress noise, the error is averaged over some length of time, and the average is used to establish the frequency of the oscillator.
If the original signal is well behaved (stable in frequency), the VCO will need little information to be able to track the input signal, and that information can be obtained by averaging for a long period of time, thereby eliminating noise that could be very large.
In data storage or communication systems, data is written using various modulation schemes. On the reading end, a receiver is responsible for recovering the data and clock (demodulation). Phase lock loops are used to lock onto the incoming data and allow separation of data and clock. As shown in FIG. 1, a typical phase lock loop is an analog system which has a VCO whose input is driven by the output of a filter of the measured phase error. The VCO can abjust frequency to match the incoming data frequency, which may vary in data storage systems due to speed variations in the head to media motion. In addition to matching the incoming frequency, the VCO will adjust its phase to match the phase on the incoming data until there is no difference ideally between the VCO output and the incoming data. The filter gain and characteristics are chosen to ensure that the VCO output will "lock" onto the input signal over a reasonable frequency range. The phase comparator may be an analog circuit, or in the case of digital communications or storage, it is typically a small digital logic circuit.
As shown in FIG. 1 the units of gain for each function in the loop are indicated. Note, particularly, that the phase detector converts phase to voltage and that the VCO converts voltage to the time derivative of phase (i.e., frequency). This has the important consequence that the VCO is actually an integrator; a fixed input voltage error produces a linearly rising phase error at the VCO output. Also, note that if the VCO frequency matches the incoming signal frequency, but there is a phase difference, the phase comparator and filter will force the VCO to go out of frequency, lock momentarily until phase lock is achieved, after which the frequency will return to lock. This process may degrade performance, especially in situations wherer phase difference occurs frequently.
The analog version of the VCO may consist of a capacitor that charges up to a threshold voltage at a variable rate depending on the input voltage (V.sup.in). See FIG. 2. When the voltage reaches the threshold voltage level in the capacitor, the capacitor discharges, a pulse is output, and the charging up process begins over again. The higher the input voltage (V.sup.in), the faster the capacitor charges ("ramps up") and the more frequently pulses are output. Similarly, the lower the input voltage (V.sup.in), the slower the capacitor charges and the less frequently pulses are output from the phase lock loop. The resolution for an analog VCO is quite high and the frequency can easily be set to within 0.1% or better in most cases.
Many digital phase lock loops have been designed in the past, and they typically have a block diagram similar to the one shown in FIG. 3. A divide by N counter has been added between the VCO output and the phase detector. The divider may be implemented as a couter or as a shift register with variable taps to set its length. The divider in the phase lock loop outputs a pulse every N clocks, and the phase comparator measures whether the output pulses lead or lag the input pulses. This measure is quantized (ofter to a single bit--indicating lead or lag) and this quantized phase error is input to the digital filter.
The complexity of the filter varies depending on the amount of jitter and frequency variation expected. The output of the digital filter consists typically of two control signals, one which increments N (i.e., slows down the divider) and one which decrements N (i.e., speeds up the divider). The nominal value of N is set by the expected number of clocks per unit time. Unless N is extremely large, the frequency resolution of this type of system is very coarse and it is impossible to lock frequency to an accuracy better than 1/N. To avoid this problem (i.e., to make N large) requires a very high clock rate which may not be feasible.